1. Field of the Invention
The present invention relates generally to the art of microelectronic integrated circuits, and more specifically to a microelectronic integrated circuit structure and method for routing wires between cells of the circuit.
2. Description of the Related Art
Microelectronic integrated circuits consist of a large number of electronic components fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric layout known as a layout. A layout consists of planar geometric shapes in several layers.
The layout is evaluated to ensure that it meets all of the design requirements. The result is a set of design files collected in an unambiguous representation known as an intermediate form that describes a layout. The design files are converted into pattern generator files used to produce patterns, known as masks, by an optical or electron beam generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires highly exacting details about geometric patterns and the separation between them. The process of converting the specifications of an electrical circuit into a layout is known as the physical design. Physical design tends to be a tedious and error-prone process due to the tight tolerance requirements and the minuteness of the individual components.
Currently utilized minimum geometric feature sizes of components used in microelectronic integrated circuit fabrication are on the order of 0.5 microns. It is anticipated that the feature size may be reduced to 0.1 microns within several years, permitting fabrication of as many as 4.5 million transistors or one million logic gates on a 25 millimeter by 25 millimeter chip. This feature size improvement trend is expected to continue, with even smaller feature geometries and more circuit elements available on an integrated circuit. Larger die or chip sizes will permit far greater numbers of circuit elements.
Each microelectronic circuit cell includes a plurality of pins or terminals, each of which is connected to pins or terminals of other cells via an electrical interconnect wire or net. A goal of the optimization process is to determine a cell placement such that all of the required interconnects can be made, and the total wirelength and interconnect congestion are minimized.
As illustrated in FIG. 1, a conventional microelectronic integrated circuit 10 comprises a substrate 12 on which a large number of microelectronic circuits are formed. These circuits include large functional macroblocks such as indicated at 14 which may be central processing units, input-output devices, or the like. A typical integrated circuit further comprises a large number of cells 16 arranged in the areas of the substrate 12 not occupied by macroblocks.
The cells may comprise individual logic gates, or more preferably may each compromise a plurality of logic gates that are interconnected to form functional blocks. A cell library consisting of standardized cells that perform desired logical operations are typically provided and combined with other cells to form an integrated circuit having the desired functionality.
The cells 16 have terminals 18 to provide interconnections to other cells 16 on the substrate 12. Interconnections have typically been made via vertical electrical conductors 20 and horizontal electrical conductors 22 that extend between the terminals 18 of the cells in such a manner as to achieve the interconnections required by the netlist of the integrated circuit 10. Other systems have connected cells via electrical conductors which are not orthogonally oriented, and thus interconnections between the various cells of a net may be multidirectional.
In typical conventional integrated circuit design, the electrical conductors 20 and 22 were formed in vertical and horizontal routing channels in a rectilinear (Manhattan) pattern.
Pins or terminals of prior systems were routed in two steps. First, a global router would plan the general location of wires on the layout. Second, a more detailed routing would be prepared by a channel router. With more routing layers becoming available and process technology improving, as well as increases in the number and of cells and corresponding decrease in feature size, it becomes highly desirable to increase the portion of the chip area used for active components as opposed to wiring. As chip utilization reaches 100 per cent, the physical routing channels tend to disappear and the artificial importance of channel routing becomes insignificant.
The prior art method of hierarchal layout has proven to be inadequate from a runtime standpoint to significantly improve routing for chips having large and complex layouts.
Programs used to route integrated circuits in the two step process described above have been utilized on a single processor. As chip size and complexity continue to increase, the time required to route a chip on a single processor is becoming too long for an efficient design cycle in spite of ever increasing processing speed and efficiency.
It is therefore an object of the current invention to provide a system able to provide detail routing for an entire integrated circuit chip in a single step, i.e. routing the entire chip at the detail level in a single operation.
It is another object of the current invention to provide a system of routing which avoids the extensive time associated with performing the routing function using a single processor.